The process of developing a chip typically begins with specifying the chip's function in a high level design language (HDL). After verification, the HDL specified design is synthesized into a hardware design that can be manufactured in a selected technology process based on a library of logic cells for the chosen technology. To verify the timing and functionality of the synthesized design, software models of the logic cells and interconnections between the logic cells are used. In the synthesis process, if a non optimal use of a library logic cell is needed to implement a specified function, then a number of inputs to the logic cell may be tied together to create the desired function. For example, if a three input AND function is required and the closest library cell is a four input AND cell, then two inputs to the four input AND cell may be tied together to create the three input AND function.
Logic cells with input pins tied together present a unique challenge for delay calculation and timing analysis. Due to limitations in software model characterization of logic cells, cell delay calculation models do not fully capture the impact of simultaneously switching inputs on the delays and transition times of output signals. This is because delay calculation model tables are characterized on an input pin to output pin basis, keeping adjacent pins at a non-blocking constant value during the characterization simulations. This approach leads to calculated delays and transitions through such cells with tied input pins which are much slower than actual silicon behavior. Analog simulations have shown that the actual delays can be as much as 43% faster in a 130 nm process, for example, as compared to the delays calculated by the current delay calculation models. In addition, incorrect delays are calculated for fan out signal paths associated with at least one cell connection made through tied input pins. The calculations for the signal paths through all of the connected cells are affected by the one tied input pin connection due to slower slopes used in the delay calculations. The incorrectly calculated delays may cause hold time analysis for signal paths containing the tied input logic cells to be incorrect and these signal paths may then present a high risk of hold time failure. The magnitude of the timing problem is amplified when numerous tied input logic cells are present in synthesized designs. Moreover, multiple such tied input logic cells may be found in single timing paths. Such problems occur due to a combination of inherent limitations in the synthesis process, limited choices of logic cell types in technology libraries, and restrictive design styles, for example.